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ispLSI 1048E
(R)
In-System Programmable High Density PLD Functional Block Diagram
Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 A0
Output Routing Pool
Features
* HIGH DENSITY PROGRAMMABLE LOGIC -- 8,000 PLD Gates -- 96 I/O Pins, Twelve Dedicated Inputs -- 288 Registers -- High-Speed Global Interconnects -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- Functionally and Pin-out Compatible to ispLSI 1048C * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 125 MHz Maximum Operating Frequency --
Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0
A3 A4 A5 A6 A7
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool
D ES IG N
Logic Array
DQ DQ
A2
D5 D4 D3 D2 D1 D0
GLB
DQ
C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool
CLK
-- TTL Compatible Inputs and Outputs -- Electrically Eraseable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture * IN-SYSTEM PROGRAMMABLE -- In-System Programmable (ISPTM) 5V Only -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
Description
48
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Enhanced Pin Locking Capability -- Four Dedicated Clock Input Pins
EA
-- Reprogram Soldered Devices for Faster Prototyping
The ispLSI 1048E is a High Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1048 architecture, the ispLSI 1048E device adds two new global output enable pins and two additional dedicated inputs. The basic unit of logic on the ispLSI 1048E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 1048E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global Interconnectivity
U
Copyright (c) 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SE
-- Lead-Free Package Options
is pL
-- Programmable Output Slew Rate Control to Minimize Switching Noise
SI
-- Synchronous and Asynchronous Clocks
10
FO
R
N
EW
tpd = 7.5 ns Propagation Delay
0139G1A-isp
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
1048e_12
1
Output Routing Pool
A1
DQ
S
D6
D7
Specifications ispLSI 1048E
Functional Block Diagram
Figure 1. ispLSI 1048E Functional Block Diagram
I/O I/O I/O I/O 95 94 93 92 RESET
GOE 0 GOE 1
I/O I/O I/O I/O 91 90 89 88
I/O I/O I/O I/O 87 86 85 84
I/O I/O I/O I/O 83 82 81 80
IN IN 11 10
I/O I/O I/O I/O 79 78 77 76
I/O I/O I/O I/O 75 74 73 72
I/O I/O I/O I/O 71 70 69 68
I/O I/O I/O I/O 67 66 65 64
IN 9
IN 8
Input Bus Generic Logic Blocks (GLBs) F7 F6 Output Routing Pool (ORP) F5 F4 F3 F2 F1 F0 E7 E6
Input Bus Output Routing Pool (ORP) E5 E4 E3 E2
ES IG N
E1 E0 D7 D6 D5 D4 D3 D2 D1 D0
D
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
A0 A1
Output Routing Pool (ORP)
EW
lnput Bus
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 MODE/IN 1
A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7
N
Global Routing Pool (GRP)
FO
R
C0
C1
C2
C3
C4
C5
C6
C7
Clock Distribution Network
Output Routing Pool (ORP) Megablock Input Bus
ispEN
IN 2 SDO/ IN 3
Output Routing Pool (ORP) Input Bus
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
48
I/O I/O I/O I/O 16 17 18 19
I/O I/O I/O I/O 20 21 22 23
I/O I/O I/O I/O 24 25 26 27
EA
I/O I/O I/O I/O 28 29 30 31
IN SCLK/ I/O I/O I/O I/O 4 IN 5 32 33 34 35
I/O I/O I/O I/O 36 37 38 39
I/O I/O I/O I/O 40 41 42 43
I/O I/O I/O I/O 44 45 46 47
YYYY 0123
0139F(2)-48B-isp
10
Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1048E device contains six Megablocks.
U
SE
The device also has 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise.
pL
The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1048E device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.
is
SI
2
S
IN 7 IN 6 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48
Specifications ispLSI 1048E
Absolute Maximum Ratings 1
Supply Voltage Vcc. ................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
DC Recommended Operating Conditions
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial
EW
D
pf pf
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
N
ES IG N
MIN. 4.75 4.5 0 2.0 MAX. 5.25 5.5 0.8 Vcc+1
UNITS Years Cycles
FO
VIL VIH
R
VCC
TA = 0C to + 70C TA = -40C to + 85C
Table 2-0005/1048E
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
EA
10
C1 C2
48
PARAMETER Y0 Clock Capacitance
TYPICAL 8 15
UNITS
TEST CONDITIONS VCC = 5.0V, VPIN = 2.0V VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1048E
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
pL
PARAMETER
SI
Data Retention Specifications
MINIMUM 20 10000 MAXIMUM - -
Data Retention
is
Erase/Reprogram Cycles
Table 2-0008/1048E
U
SE
3
S
UNITS V V V V
Specifications ispLSI 1048E
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 3 ns 10% to 90% 1.5V 1.5V See Figure 2
Table 2-0003/1048E
Figure 2. Test Load
+ 5V R1 Device Output
R2
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
EW
*CL includes Test Fixture and Probe Capacitance.
0213a
Table 2-0004a
Over Recommended Operating Conditions
10
48
DC Electrical Characteristics
SYMBOL PARAMETER Output Low Voltage Output High Voltage
EA
FO
C
R
N
D
CONDITION IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) MIN. - 2.4 - - - - - - - TYP. - - - - - - - 175
3
SE
VOL VOH IIL IIH IIL-isp IIL-PU IOS1
ES IG N
CL*
0.4 - -10 10 -150 -150 -200 -
MAX. UNITS V V A A A A mA mA
Input or I/O High Leakage Current 3.5V VIN VCC I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current
is
ispEN Input Low Leakage Current 0V VIN VIL 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V Commercial
175 - mA Industrial fCLOCK = 1 MHz 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems Table 2-0007/1048E by tester ground degradation. Characterized but not 100% tested. 2. Measured using twelve 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC .
ICC2, 4
U
pL
Input or I/O Low Leakage Current
SI
4
S
Test Point
Specifications ispLSI 1048E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND.
4
#
2
DESCRIPTION
1
-125 - - 125.0
1 tsu2 + tco1
-100 - - 100.0 71.0 6.5 - 125.0 10.0 12.5 - - - - - -
-90 10.0 12.5 - -
MIN. MAX. MIN. MAX. MIN. MAX. 7.5 10.0 - - - - 4.5 - - - - 12.0 12.0 7.0 7.0 - - - - 5.5
UNITS ns
10
tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3
1. 2. 3. 4.
A A A - - - A - - - - A - B C B C - - - -
1 2 3 4 5 6 7 8 9
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback 3 Clock Frequency with External Feedback ( Clock Frequency, Max. Toggle
ES IG N
90.9 71.0 6.5 - 125.0 - - 6.5 - - 7.5 - 13.5 - 15.0 15.0 9.0 9.0 - - - - 6.5 - - 7.5 - 13.5 - 15.0 15.0 9.0 9.0 - - - - 0.0 7.5 - 0.0 - 6.5 - - - - 4.0 4.0 4.0 0.0
)
91.0 167.0 5.5 - 0.0 6.5 - - - - - - 3.0 3.0 0.0 5.0
(
1 twh + twl
)
GLB Reg. Setup Time before Clock,4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
D
0.0 7.5 - 0.0 - 6.5 - - - - 4.0 4.0 3.5 0.0
EW
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable
N
10.0
R
FO
18 External Synchronous Clock Pulse Duration, High 20 21
EA
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0
48
19 External Synchronous Clock Pulse Duration, Low
U
SE
is
pL
SI
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
Table 2-0030A/1048E
5
S
ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Specifications ispLSI 1048E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND.
4
#
2
DESCRIPTION
1
-70 - -
1 tsu2 + tco1
-50 - - 50.0 20.0 24.5 - -
10
tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3
1. 2. 3. 4.
A A A - - - A - - - - A - B C B C - - - -
1 2 3 4 5 6 7 8 9
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle
3
15.0 18.5 - - - -
ES IG N
42.0 77.0 12.0 - 0.0 14.5 - 0.0 - 13.0 - - - - 6.5 6.5 6.5 0.0 - - 7.0 - - 9.0 - 15.0 - 18.0 18.0 12.0 12.0 - - - - 9.5 - - 12.0 - 20.5 - 24.0 24.0 16.0 16.0 - - - -
70.0
Clock Frequency with External Feedback (
)
56.0 9.0 -
( twh 1+ twl )
100.0
GLB Reg. Setup Time before Clock,4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
D EW
0.0 11.0 - 0.0 - 10.0 - - - - 5.0 5.0 4.0 0.0
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable
N
R
FO
EA
18 External Synchronous Clock Pulse Duration, High 20 21 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
48
19 External Synchronous Clock Pulse Duration, Low
U
SE
is
pL
SI
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
Table 2-0030B/1048E
6
S
ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
MIN. MAX. MIN. MAX.
UNITS
Specifications ispLSI 1048E
Internal Timing Parameters1
PARAMETER Inputs #2 -125 DESCRIPTION -100 -90 UNITS
MIN. MAX. MIN. MAX. MIN. MAX. - - 3.0 0.0 - - - - 0.3 1.9 - - 4.6 4.6 2.3 1.8 2.0 2.3 2.8 4.9 3.9 4.0 3.6 5.0 5.0 0.4 - - 2.3 4.9 3.9 5.4 4.0 1.0 0.0 - - 0.3 2.3 - - - 0.5 -
28 Dedicated Input Delay 29 GRP Delay, 1 GLB Load 30 GRP Delay, 4 GLB Loads 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads 33 GRP Delay, 48 GLB Loads
D
- - - - - - - - - - - - 0.5 5.3 - - - - 3.5 - -
tiobp tiolat tiosu tioh tioco tior tdin
GRP
23 I/O Latch Delay 24 I/O Register Setup Time before Clock 25 I/O Register Hold Time after Clock 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay
ES IG N
- 2.5 - 4.0 - - -0.5 5.0 5.0 2.7 5.0 5.0 - - - - - - - - - - - - 0.1 6.4 - - - - 4.0 - - 2.9 2.2 2.4 2.7 3.3 5.7 5.4 6.3 6.5 6.5 7.3 0.4 - - 2.0 6.3 5.0 5.7 5.2 1.0 0.0 1.9 2.4 2.6 3.0 5.4 5.3 5.3 4.6 5.8 6.3 1.0 - - 2.5 6.2 4.5 7.2 4.7 1.0 0.0
22 I/O Register Bypass
3.5 - -
0.0
R
tgrp1 tgrp4 tgrp8 tgrp16 tgrp48
GLB
EW
- - - - - -
N
is
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
34 4 Product Term Bypass Path Delay (Combinatorial) 35 4 Product Term Bypass Path Delay (Registered)
FO
EA
36 1 Product Term/XOR Path Delay
- - - - 0.1 4.5 - - - - 2.9 - -
37 20 Product Term/XOR Path Delay 38 XOR Adjacent Path Delay
48
3
39 GLB Register Bypass Delay
40 GLB Register Setup Time before Clock 41 GLB Register Hold Time after Clock 42 GLB Register Clock to Output Delay 43 GLB Register Reset to Output Delay 44 GLB Product Term Reset to Register Delay 45 GLB Product Term Output Enable to I/O Cell Delay 46 GLB Product Term Clock Delay 47 ORP Delay 48 ORP Bypass Delay
10
SI
pL
torp torpbp
SE
U
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/1048E
7
S
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Specifications ispLSI 1048E
Internal Timing Parameters1
PARAMETER Inputs #2 -70 DESCRIPTION -50 UNITS
MIN. MAX. MIN. MAX. - - 4.1 - - - 0.6 3.6 - - - - 6.5 - - 0.7 4.7 - -
28 Dedicated Input Delay 29 GRP Delay, 1 GLB Load 30 GRP Delay, 4 GLB Loads 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads 33 GRP Delay, 48 GLB Loads
D EW
- - - - - - - - - - - 0.1 8.5 - - - - 5.1 - -
tiobp tiolat tiosu tioh tioco tior tdin
GRP
22 I/O Register Bypass 23 I/O Latch Delay 24 I/O Register Setup Time before Clock 25 I/O Register Hold Time after Clock 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay
ES IG N
-0.7 6.0 6.0 4.3 7.0 7.0 - - - - - - - - - - - - 0.0 11.5 - - - - 6.9 - - 6.1 5.1 5.4 5.8 6.6 9.8 10.7 9.2 10.5 10.5 11.7 2.2 - - 3.0 7.3 7.9 10.0 8.3 2.5 0.0 3.5 3.7 4.1 4.8 7.5 8.5 7.4 8.4 8.4 9.4 1.6 - - 2.0 6.3 6.1 6.8 6.4 2.0 0.0
-0.6
R
tgrp1 tgrp4 tgrp8 tgrp16 tgrp48
GLB
N
ORP
SE
torp torpbp
is
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
34 4 Product Term Bypass Path Delay (Combinatorial) 35 4 Product Term Bypass Path Delay (Registered) 36 1 Product Term/XOR Path Delay 38 XOR Adjacent Path Delay
3
FO
EA
37 20 Product Term/XOR Path Delay 39 GLB Register Bypass Delay
48
41 GLB Register Hold Time after Clock
10
40 GLB Register Setup Time before Clock 42 GLB Register Clock to Output Delay 43 GLB Register Reset to Output Delay 44 GLB Product Term Reset to Register Delay 45 GLB Product Term Output Enable to I/O Cell Delay 46 GLB Product Term Clock Delay 47 ORP Delay 48 ORP Bypass Delay
SI
pL
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
U
Table 2-0036B/1048E
8
S
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Specifications ispLSI 1048E
Internal Timing Parameters1
PARAMETER Outputs 50 Output Slew Limited Delay Adder 51 I/O Cell OE to Output Enabled 52 I/O Cell OE to Output Disabled 53 Global OE 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 56 Clock Delay, Clock GLB to Global GLB Clock Line 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 59 Global Reset to GLB and I/O Registers - - - - 0.9 0.9 0.8 0.0 0.8 - 10.0 4.3 4.3 2.7 0.9 0.9 1.8 0.0 1.8 - - - - # DESCRIPTION -125 -100 -90 MIN. MAX. MIN. MAX. MIN. MAX. - 1.3 - 2.0 10.0 5.1 5.1 3.9 - - - - 1.7 6.4 6.4 UNITS
ES IG N
12.0 - 2.6 2.0 2.8 2.8 2.0 1.8 0.0 1.8 4.3 2.8 0.8 0.0 0.8 - 2.8 1.8 0.5 1.8 4.5
tob tsl toen todis tgoe
Clocks
49 Output Buffer Delay
Global Reset
R
tgr
N
tgy0 tgy1/2 tgcp tioy2/3 tiocp
D
2.0 0.8 0.0 0.8 -
2.0
EW
2.8
U
SE
is
pL
SI
10
48
EA
FO
1. Internal timing parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
Table 2-0037A/1048E
9
S
ns ns ns ns ns ns ns ns ns ns ns
Specifications ispLSI 1048E
Internal Timing Parameters1
PARAMETER Outputs # DESCRIPTION -70 -50 UNITS
MIN. MAX. MIN. MAX. - - - - - 2.2 12.0 6.9 6.9 5.1 - - - - 3.2 7.9 7.9
50 Output Slew Limited Delay Adder 51 I/O Cell OE to Output Enabled 52 I/O Cell OE to Output Disabled 53 Global OE 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 56 Clock Delay, Clock GLB to Global GLB Clock Line 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 59 Global Reset to GLB and I/O Registers
ES IG N
12.0 - 8.1 2.8 2.8 1.8 0.6 1.8 4.5 3.3 3.3 0.8 0.0 0.8 - 3.3 3.3 1.8 0.7 1.8 7.5
tob tsl toen todis tgoe
Clocks
49 Output Buffer Delay
Global Reset
R
tgr
N
tgy0 tgy1/2 tgcp tioy2/3 tiocp
D
2.8 2.8 0.8 0.1 0.8 -
EW
U
SE
is
pL
SI
10
48
EA
FO
1. Internal timing parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
Table 2-0037B/1048E
10
S
ns ns ns ns ns ns ns ns ns ns ns
Specifications ispLSI 1048E
ispLSI 1048E Timing Model
I/O Cell GRP Feedback Ded. In #34 GRP4 #30 GRP Loading Delay #29, 31-33 Comb 4 PT Bypass GLB Reg Bypass #39 GLB Reg Delay D RST Reset #59 #40 - 43 Q ORP Bypass #48 #49, 50 GLB ORP I/O Cell
#28 I/O Reg Bypass #22 Input D Register Q RST #23 - 27
#35 20 PT XOR Delays #36 - 38
ORP Delay #47
#59
Clock Distribution Y1,2,3 #55 - 58
EW
Control RE PTs OE #44 - 46 CK
D
0491
Y0 GOE 0,1
#54 #53
Derivations of tsu, th and tco from the Product Term Clock 1 tsu
= = = 2.2 ns = = = = 3.5 ns = = = = 10.9 ns =
th
tco
Derivations of tsu, th and tco from the Clock GLB 1
SE
th
= = = 2.2 ns = = = = 9.6 ns =
U
tco
1. Calculations are based upon timing specifications for the ispLSI 1048E-125.
Table 2-0042/1048E
is
tsu
= = = 3.4 ns =
pL
Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #37) + (#40) - (#54 + #42 + #56) (0.3 + 2.0 + 5.0) + (0.1) - (0.9 + 2.3 + 0.8) Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#54 + #42 + #56) + (#41) - (#22 + #30 + #37) (0.9 + 2.3 + 1.8) + (4.5) - (0.3 + 2.0 + 5.0)
Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #42 + #56) + (#42) + (#47 + #49) (0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
SI
Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
10
48
Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 2.0 + 4.0) + (4.5) - (0.3 + 2.0 + 5.0)
EA
Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #37) + (#40) - (#22 + #30 + #46) (0.3 + 2.0 + 5.0) + (0.1) - (0.3 + 2.0 + 2.9)
FO
11
R
N
ES IG N
#51, 52
I/O Pin (Input)
Reg 4 PT Bypass
S
I/O Pin (Output)
Specifications ispLSI 1048E
Maximum GRP Delay vs. GLB Loads
10 9 8
GRP Delay (ns)
ispLSI 1048E-50
7 6 5 4 3 2 1 1 4 8 16 GLB Loads 32 48 ispLSI 1048E-90/100 ispLSI 1048E-125
0127A/1048E
Figure 3. Typical Device Power Consumption vs fmax
380 340
ICC (mA)
220 180
pL
SI
0
10
260
20
48
300
40
EA
ispLSI 1048E
60
80
FO
Power consumption in the ispLSI 1048E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used.
100
R
Figure 3 shows the relationship between power and operating speed.
120
is
fmax (MHz)
Notes: Configuration of twelve 16-bit counters, Typical current at 5V, 25C
ICC can be estimated for the ispLSI 1048E using the following equation:
U
ICC = 20 + (# of PTs * 0.42) + (# of nets * Max. freq * 0.010)
Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 4 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
SE
N
Power Consumption
140
EW
D
0127B/1048E
12
ES IG N
S
ispLSI 1048E-70
Specifications ispLSI 1048E
Pin Description
NAME
I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 GOE0, GOE1 IN 2, IN 4 IN 6 - IN 11 ispEN SDI/IN 01
PQFP / TQFP PIN NUMBERS
21, 27, 34, 40, 52, 58, 66, 72, 85, 91, 98, 104, 117, 123, 2, 8, 64, 47, 84, 18 22, 28, 35, 41, 53, 59, 67, 73, 86, 92, 99, 105, 118, 124, 3, 9, 114 51 110, 111, 115, 116, 14 23, 29, 36, 42, 54, 60, 68, 74, 87, 93, 100, 106, 119, 125, 4, 10, 24, 30, 37, 43, 55, 61, 69, 75, 88, 94, 101, 107, 120, 126, 5, 11, 25, 31, 38, 44, 56, 62, 70, 76, 89, 95, 102, 108, 121, 127, 6, 12, 26, 32, 39, 45, 57, 63, 71, 77, 90, 96, 103, 109, 122, 128, 7, 13
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
Dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. When low, the MODE, SDI, SDO and SCLK controls become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the ISP state machine. When ispEN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. When ispEN is high, it functions as a dedicated input pin. Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated input pin. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device.
20
MODE/IN 11
46
SDO/IN 31
50
SCLK/IN 51
78
RESET Y0 Y1
19 15 83
Y2
Y3
SE
is
pL
80
79
U
GND VCC
1, 97, 16,
SI
17, 112 48,
10
33, 82,
49, 113
48
EA
65,
81,
FO
Ground (GND) VCC
Table 2 - 0002C-48E
1. Pins have dual function capability.
13
R
N
EW
Global Output Enable input pins.
D
ES IG N
S
Specifications ispLSI 1048E
Pin Configuration
ispLSI 1048E 128-Pin PQFP Pinout Diagram
I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 IN 10 IN 9 GOE 1 VCC GND IN 8 IN 7 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND
is
SE
GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 1MODE/IN 1 IN 2 VCC GND 1SDO/IN 3 IN 4 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GOE 0
pL
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
SI
GND I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 IN 11 Y0 VCC GND ispEN RESET 1SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Top View
10
48
EA
FO
ispLSI 1048E
R
N
EW
D
14
U
1. Pins have dual function capability.
ES IG N
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 Y1 VCC GND Y2 Y3 SCLK/IN 51 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 GND
S
0124-48C
Specifications ispLSI 1048E
Pin Configuration
ispLSI 1048E 128-Pin TQFP Pinout Diagram
I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 IN 10 IN 9 GOE 1 VCC GND IN 8 IN 7 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND
is
U
1. Pins have dual function capability.
0124-48/TQFP
GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 1MODE/IN 1 IN 2 VCC GND 1SDO/IN 3 IN 4 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GOE 0
SE
pL
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
SI
GND I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 IN 11 Y0 VCC GND ispEN RESET 1SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Top View
10
48
EA
FO
ispLSI 1048E
15
R
N
EW
D
ES IG N
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 Y1 VCC GND Y2 Y3 SCLK/IN 51 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 GND
S
Specifications ispLSI 1048E
Package Thermal Characteristics
For the ispLSI 1048E-125LT, it is strongly recommended that the actual Icc be verified to ensure that the maximum junction temperature (TJ) with power supplied is not exceeded. Depending on the specific logic design and clock speed, airflow may be required to satisfy the maximum allowable junction temperature (TJ) specification. Please refer to the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM for additional information on calculating TJ.
Part Number Description
ispLSI 1048E - XXX
Device Family Device Number Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 90 = 90 MHz fmax 70 = 70 MHz fmax 50 = 50 MHz fmax
X
X
X
N
Package Q = PQFP T = TQFP QN = Lead-Free PQFP TN = Lead-Free TQFP Power L = Low
ispLSI 1048E Ordering Information Conventional Packaging
FAMILY fmax (MHz) 125 125 100 100 ispLSI 90 90 70 70 50 tpd (ns) 7.5 7.5 10 10
EA
COMMERCIAL
ORDERING NUMBER ispLSI 1048E-125LQ ispLSI 1048E-125LT ispLSI 1048E-100LQ ispLSI 1048E-100LT ispLSI 1048E-90LQ ispLSI 1048E-90LT ispLSI 1048E-70LQ ispLSI 1048E-70LT ispLSI 1048E-50LQ ispLSI 1048E-50LT PACKAGE 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP
Table 2-0041A/1048E
pL
is
50
SE
SI
10
10 10 15 15 20 20
48
INDUSTRIAL
fmax (MHz) 70 50 tpd (ns) 15 20 ORDERING NUMBER ispLSI 1048E-70LQI* ispLSI 1048E-50LQI* PACKAGE 128-Pin PQFP 128-Pin PQFP
Table 2-0041B/1048E
FAMILY ispLSI
U
*Use 1048E-70 for new 1048E-50 designs.
FO
16
R
EW
D
Grade Blank = Commercial I = Industrial
ES IG N
S
Specifications ispLSI 1048E
ispLSI 1048E Ordering Information (Cont.) Lead-Free Packaging
COMMERCIAL
125 125 100 100 ispLSI 90 90 70 70 50 50 7.5 7.5 10 10 10 10 15 15 20 20 ispLSI 1048E-125LQN ispLSI 1048E-125LTN ispLSI 1048E-100LQN ispLSI 1048E-100LTN ispLSI 1048E-90LQN ispLSI 1048E-90LTN ispLSI 1048E-70LQN ispLSI 1048E-70LTN ispLSI 1048E-50LQN ispLSI 1048E-50LTN Lead-Free 128-Pin PQFP Lead-Free 128-Pin TQFP Lead-Free 128-Pin PQFP Lead-Free 128-Pin TQFP FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE
EW
INDUSTRIAL
FAMILY ispLSI fmax (MHz) 70 tpd (ns) 15
ORDERING NUMBER
N
D
Revision History
Date -- August 2006 Version 11 12
FO
R
ispLSI 1048E-70LQNI
U
SE
is
pL
SI
10
48
EA
Change Summary
Previous Lattice release. Updated for lead-free package options.
17
ES IG N
PACKAGE
Lead-Free 128-Pin PQFP Lead-Free 128-Pin TQFP Lead-Free 128-Pin PQFP Lead-Free 128-Pin TQFP Lead-Free 128-Pin PQFP Lead-Free 128-Pin TQFP
Lead-Free 128-Pin PQFP
S

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